PCK111

General description

The PCK111 is a low skew 1-to-10 differential driver, designed with clock distribution in mind. It accepts two clock sources into an input multiplexer. The PECL input signals can be either differential or single-ended if the V_BB output is used. The selected signal is fanned out to 10 identical differential outputs.

The PCK111 is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent t_PD distributions from lot to lot. The net result is a dependable, guaranteed low skew device.

To ensure that the tight skew specification is met, it is necessary that both sides of the differential output are terminated into 50 Ohm, even if only one side is being used. In most applications, all ten differential pairs will be used, and therefore terminated. In the case where fewer than ten pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10?20 ps) of the output(s) being used, which, while not being catastrophic to most designs, will mean a loss of skew margin.

The PCK111 can be used for high performance clock distribution in +3.3 V or +2.5 V systems. Designers can take advantage of the PCK111?s performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies.

The PCK111 may be driven single-endedly utilizing the V_BB bias output with the CLK0 input. If a single-ended signal is to be used, the V_BB pin should be connected to the CLK0 input and bypassed to ground via a 0.01 uF capacitor. The V_BB output can only source/sink 0.2 mA, therefore, it should be used as a switching reference for the PCK111 only. Part-to-part skew specifications are not guaranteed when driving the PCK111 single-endedly.

Features

• 85 ps part-to-part skew typical
• 20 ps output-to-output skew typical
• Differential design
• V_BB output
• Low voltage V_EE range of ?2.25 V to ?3.8 V for ECL
• Low voltage V_CC range of +2.375 V to +3.8 V for PECL
• 75 kOhm input pull-down resistors
• ECL/PECL outputs
• Form, fit, and function compatible with MC100EP111

Products/packages

Pricing/ordering/availability

Block diagrams/pinning

Design support

Application Notes

AN259_1; Applications and performance of PTN1111 and PTN2111 clock distribution devices PTN1111 and PTN2111 clock distribution devices (16-Oct-01)

Support Documents

75010459; PCK111/PCK210/PCKEL14/PCKEP14 High-performance PECL Clock Distribution Family Leaflet (2002-10-01)

75010759; PCK2111 LVDS Clock Distribution IC (2002-12-20)

75010594; PCK351 & PCK3807A LVTTL Clock Distribution ICs (2002-12-20)

Parametrics/similar products

Similar products
PCK111 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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