PCK12429

General description

The internal oscillator uses the external quartz crystal as the basis of its frequency reference. The output of the reference oscillator is divided by 16 before being sent to the phase detector.

The VCO output is scaled by a divider that is configured by either the serial or parallel interfaces. The output of this loop divider is also applied to the phase detector.

The phase detector and loop filter attempt to force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high too low) the PLL will not achieve loop lock.

The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider (N divider) is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50 pct duty cycle.

The output driver is driven differentially from the output divider, and capable of driving a pair of transmission lines terminated in 50 Ohm V_CC-2.0. The positive reference for the output driver and the internal logic is separated from the power supply for the phase-locked loop to minimize noise induced jitter.

The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. Normally, on system reset, the LOAD input is held LOW until sometime after power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[8:0] and 1:0] inputs to reduce component count in the application of the chip.

The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the programming section for more information.

The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the programming section for more information.

Features

• 25 to 400 MHz differential PECL outputs
• +-25 ps peak-to-peak output jitter
• Fully integrated phase-locked loop
• Minimal frequency over-shoot
• Synthesized architecture
• Serial 3-wire interface
• Parallel interface for power-up
• Quartz crystal interface
• Package offer: SO28, PLCC28, and LQFP32
• Operates from 3.3 V power supply

Products/packages

Pricing/ordering/availability

Block diagrams/pinning

Design support

Support Documents

75011422; New MultiMarket Products Quarterly Highlights 2.2 May 2003 (2003-06-19)

75010201; PCK12429 25-800 MHz Differential PECL Clock Generator Family Leaflet (2002-09-25)

Parametrics/similar products

Similar products
PCK12429 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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