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PCK2057
Datasheet
General description
The PCK2057 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs and one differential pair of feedback clock outputs. The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the 2-line serial interface (SDA, SCL), and the analog power input (AV DD ). The two-line serial interface (I² C) can put the individual output clock pairs in a high-impedance state. When AV DD is tied to GND, the PLL is turned off and bypassed for test purposes. The device provides a standard mode (100 kbits) I² C interface for device control. The implementation is as a slave/receiver. The serial inputs (SDA, SCL) provide integrated pull-up resistors (typically 100 kW). Two 8-bit, 2-line serial registers provide individual enable control for each output pair. All outputs default to enabled at power-up. Each output pair can be placed in a high-impedance mode, when a low-level control bit is written to the control register. The registers must be accessed in sequential order (i.e., random access of the registers is not supported). The I²C interface circuit can be supplied with either 2.5 V or 3.3 V (V DD I² C). Since the PCK2057 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power-up.
Features
- Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications supporting DDR 200/266/300/333
- Full DDR solution provided when used with PCK2002P or PCK2002PL, and PCK2022RA
- 1-to-10 differential clock distribution
- Very low jitter (< 100 ps)
- Operation from 2.2 V to 2.7 V AV DD and 2.3 V to 2.7 V V DD
- SSTL_2 interface clock inputs and outputs
- HCSL to SSTL_2 input conversion
- Test mode enables buffers while disabling PLL
- Tolerant of Spread Spectrum input clock
- 3.3 V I²C support with 3.3 V V DD I²C
- 2.5 V I²C support with 2.5 V V DD I²C
- Form, fit, and function compatible with CDCV850
Products/packages
| Type number | North American Type number | Ordering code (12NC) | Product status | Package | Packing | Marking | Chemical content | Leadfree conversion date |
|---|---|---|---|---|---|---|---|---|
| PCK2057DGG | PCK2057DGG | 9352 695 56512 | Samples available | SOT362-1
(TSSOP48) | Tube Dry Pack | Standard Marking | PCK2057DGG
| week 12, 2005 |
| PCK2057DGG | PCK2057DGG-T | 9352 695 56518 | Samples available | SOT362-1
(TSSOP48) | Reel Dry Pack, SMD, 13" | Standard Marking | PCK2057DGG
| week 12, 2005 |
Pricing/ordering/availability
| Type number | Ordering code(12NC) | Indicative price/unit($) | Region | Distributor | In stock | Order quantity | Inventory date | Buy online | Samples |
|---|---|---|---|---|---|---|---|---|---|
| PCK2057DGG | 9352 695 56512 | 2.6600 | not available | ||||||
| PCK2057DGG | 9352 695 56518 | 2.6600 | not available |
Design support
Support Documents
75014354;
Memory interface selection guide Support logic for memory modules and other memory subsystems (2005-06-01)Parametrics/similar products
| Type number | Package | Supply voltage(V) | Application | Other features | Operating temp.(Cel) | Inputs | Outputs | Output frequency range(MHz) | Jitter (pk-pk)(ps) | Output skew(ps) | Programmability | Phase offset(ps) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PCK2057DGG | SOT362-1
(TSSOP48) | 2.5 | DDR zero-delay clock distribution | individual output disable, bypass | 0~+70 | 1 x SSTL-2 | 11 x SSTL-2 | 70~190 | 75 | 75 | I2C | 270 |
Similar products
PCK2057
links to the similar products page containing an overview of products that are similar in
function or related to the type number(s) as listed on this page.
The similar products page includes products from the same catalog tree(s),
relevant selection guides and products from the same functional category.
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