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SSTL16877
Datasheet
General description
The SSTL16877 is a 14-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. VDDQ must not exceed VCC . Inputs are SSTL_2 type with VREF normally at 0.5*VDDQ . The outputs support class I which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero.
The SSTL16877 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 166 MHz will have a burst rate of 333 MHz. The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTL16877 is intended to be used for SSTL_2 input and output signals.
The device data inputs consist of differential receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs.
The clock input is fully differential to be compatible with DRAM devices that are installed on the DIMM. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CLK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device must support an asynchronous input pin (reset), which when held to the LOW state will assume that all registers are reset to the LOW state and all outputs drive a LOW signal as well.
Features
- Stub-series terminated logic for 2.5 V VDDQ (SSTL_2)
- Optimized for DDR (Double Data Rate) SDRAM applications
- Supports SSTL_2 signal inputs and outputs
- Flow-through architecture optimizes PCB layout
- Meets SSTL_2 class I and class II specifications
- Latch-up protection exceeds 500mA per JEDEC Std 17
- ESD protection exceeds 2500 V per MIL STD 833 Method 3015 and 200 V per Machine Model
- Full DDR1 PC333 solution @ 2.5 V when used with PCKV857
- Mixed 2.5 V (PC266) / 3.3 V (PC333) solution when used with PCK857
- Same form, fit, and function as SSTV16857
Products/packages
| Type number | North American Type number | Ordering code (12NC) | Product status | Package | Packing | Marking | Chemical content | Leadfree conversion date |
|---|---|---|---|---|---|---|---|---|
| SSTL16877DGG | SSTL16877DG | 9352 676 36112 | Volume production | SOT362-1
(TSSOP48) | Tube | Standard Marking | SSTL16877DGG
| |
| SSTL16877DGG | 9352 676 36118 | Volume production | SOT362-1
(TSSOP48) | Reel Pack, SMD, 13" | Standard Marking | SSTL16877DGG
| ||
| SSTL16877DGG | SSTL16877DGG-T | 9352 676 36518 | Volume production | SOT362-1
(TSSOP48) | Reel Dry Pack, SMD, 13" | Standard Marking | SSTL16877DGG
| week 20, 2005 |
| SSTL16877DGG | SSTL16877DG | 9352 676 36512 | Samples available | SOT362-1
(TSSOP48) | Tube Dry Pack | Standard Marking | SSTL16877DGG
| week 20, 2005 |
| SSTL16877DGG/G | 9352 762 77518 | Samples available | SOT362-1
(TSSOP48) | Reel Dry Pack, SMD, 13" | Standard Marking | SSTL16877DGG/G
| week 18, 2005 |
Pricing/ordering/availability
| Type number | Ordering code(12NC) | Indicative price/unit($) | Region | Distributor | In stock | Order quantity | Inventory date | Buy online | Samples |
|---|---|---|---|---|---|---|---|---|---|
| SSTL16877DGG | 9352 676 36112 | not available | |||||||
| SSTL16877DGG | 9352 676 36118 | not available | |||||||
| SSTL16877DGG | 9352 676 36518 | 1.1500 | not available | ||||||
| SSTL16877DGG | 9352 676 36512 | 1.1500 | not available | ||||||
| SSTL16877DGG/G | 9352 762 77518 | not available |
Design support
Support Documents
Parametrics/similar products
| Type number | Package | Supply voltage(V) | Application | Other features | Operating temp.(Cel) | Propagation Delay(ns) | Operating Frequency(MHz) | Inputs | Outputs | Set-up time (DATA-CLK)(ns) | Hold time (CLK-DATA)(ns) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| SSTL16877DGG | SOT362-1
(TSSOP48) | 2.5 | DDR SDRAM register | master reset | 0~+70 | 2.4 | 200 | 14 x SSTL-2 | 14 x SSTL-2 | 0.2 | 1.2 |
| SSTL16877DGG/G | SOT362-1
(TSSOP48) | 2.5 | DDR SDRAM register | master reset | 0~+70 | 2.4 | 200 | 14 x SSTL-2 | 14 x SSTL-2 | 0.2 | 1.2 |
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SSTL16877
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