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SSTUB32866
General description
The SSTUB32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC standard for the SSTUB32866 registered buffer. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated as Register A or Register B on the DIMM.
The SSTUB32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit.
The SSTUB32866 is packaged in a 96-ball, 6 x 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm x 5.5 mm).
Features
- Configurable register supporting DDR2 up to 800 MT/s Registered DIMM applications
- Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode
- Controlled output impedance drivers enable optimal signal integrity and speed
- Meets or exceeds SSTUB32866 JEDEC standard speed performance
- Supports up to 450 MHz clock frequency of operation
- Optimized pinout for high-density DDR2 module design
- Chip-selects minimize power consumption by gating data outputs from changing state
- Supports SSTL_18 data inputs
- Checks parity on the DIMM-independent data inputs
- Partial parity output and input allows cascading of two SSTUB32866s for correct parity error processing
- Differential clock (CK and CK) inputs
- Supports LVCMOS switching levels on the control and RESET inputs
- Single 1.8 V supply operation (1.7 V to 2.0 V)
- Available in 96-ball, 13.5 mm x 5.5 mm, 0.8 mm ball pitch LFBGA package
Products/packages
| Type number | North American Type number | Ordering code (12NC) | Product status | Package | Packing | Marking | Chemical content | Leadfree conversion date |
|---|---|---|---|---|---|---|---|---|
| SSTUB32866EC/G | SSTUB32866EC/G-T | 9352 812 79518 | Volume production | SOT536-1
(LFBGA96) | Tape reel smd | Standard Marking | SSTUB32866EC/G
| Always Pb-free |
| SSTUB32866EC/S | 9352 831 44518 | Volume production | SOT536-1
(LFBGA96) | Tape reel smd | Standard Marking | SSTUB32866EC/S
| Always Pb-free |
Pricing/ordering/availability
| Type number | Ordering code(12NC) | Indicative price/unit($) | Region | Distributor | In stock | Order quantity | Inventory date | Buy online | Samples |
|---|---|---|---|---|---|---|---|---|---|
| SSTUB32866EC/G | 9352 812 79518 | Order samples | |||||||
| SSTUB32866EC/S | 9352 831 44518 | not available |
Applications
- 400 MT/s to 800 MT/s DDR2 registered DIMMs desiring parity checking functionality
Parametrics/similar products
| Type number | Package | Supply voltage(V) | Application | FEATURES | Operating temp.(Cel) | Propagation Delay(ns) | Operating Frequency(MHz) | Inputs | Outputs |
|---|---|---|---|---|---|---|---|---|---|
| SSTUB32866EC/G | SOT536-1
(LFBGA96) | 1.7~2.0 | DDR2 400-800 Registered DIMMs | Parity checking | 0~+70 | 1.1~1.5 | 0~500 | 14 (1:2) or 25 (1:1) x SSTL_18 | 25 (1:1) or 28 (1:2) x SSTL_18 |
| SSTUB32866EC/S | SOT536-1
(LFBGA96) | 1.7~2.0 | DDR2 400-800 Registered DIMMs | Parity checking | 0~+85 | 1.1~1.5 | 0~500 | 14 (1:2) or 25 (1:1) x SSTL_18 | 25 (1:1) or 28 (1:2) x SSTL_18 |
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SSTUB32866
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